The Image Prism
This talk describes a variety of custom designed integrated circuits I
developed for the earliest SUN workstation developed at Stanford. These chips
accelerate common, low-level bitmap graphic functions. They are among the
earliest bitmap graphic chips developed and include a RasterOp processor and a
unique register file called The Image Prism. The RasterOp processor replaced
two-thirds of the circuitry on the original single printed circuit board of
that first SUN workstation. It consisted of an early 68000 processor and
bitmap graphic frame buffer display controller hardware that was the heart of
the original SUN workstation. The RasterOp processor provided alignment,
masking, and merging of four images at approximately 4 nanoseconds per pixel.
That chip also supported nibble-mode, Read-Modify-Write DRAM memory and was
fast enough to provide full memory coverage without need for a separate
refresh cycle.
These chips led to the development of a network-oriented bitmap graphic
terminal designed for Xerox PARC. This graphics terminal precedes the
X-terminal by a number of years. Like many PARC projects, it was never fully
developed or commercialized. The instruction set was influenced by the
emerging RISC ideas for computer architecture. Specifically, the instruction
set implemented the generator set of an abstract algebra for bitmap graphics.
This particular algebra (A Bitmap Calculus) was formulated by Leo Guibas and
Jorge Stolfi. It included specific operations for rotating and mirroring
bitmap images (the Orthogonal Image Transformations). These are fundamental
operations required for common printing functions. This work also coincides
with the earliest commercialization of the laser printer.
The Image Prism, an IC specifically designed for rotating and mirroring
images, enables the fastest known algorithm for performing these bitmap
graphic operations. It was patented by Stanford University. AMD produced a
commercial implementation of the chip. The Image Prism has been used as a CAD
benchmark for a variety of competitions for the automatic layout of integrated
circuits.
